This invention relates to improved circuitry and power bus connections thereof for multiple off chip drivers (OCDs) of an integrated circuit (IC) to enable these drivers to provide synchronized multiple binary output signals (ones, xe2x80x9c1""sxe2x80x9d, and zeros, xe2x80x9c0""sxe2x80x9d) from an electronic memory unit, such as dynamic random access memory (DRAM), with minimal synchronous switching output timing (TSSO) errors at very high clock rates.
Dynamic random access memories (DRAMs) contain many millions of memory cells on a single integrated circuit (IC) chip and are capable of operating at very high clock rates. It is customary to provide on a separate integrated circuit an array of input receivers and output drivers to provide input binary signals to be stored in the memory and subsequently to output these binary signals to other circuitry as desired. In order to take full advantage of the high switching speed capability of a DRAM, the drivers, which are denoted as off chip drivers (OCDs), need to be capable of operating at very high clock rates, for example, at hundreds of megahertz.
Each of the off chip drivers on an IC chip, which itself is connected via pins and bond wires to other circuitry, is connected between at least two voltage supply buses on the chip which power the drivers. But because of physical constraints and space considerations in the layout of the drivers on the chip, some of the drivers are connected closer to the input ends of the voltage supply buses and other are connected much further away. Even though distances can be very short (e.g., a few millimeters or less), the inherent electrical inductances of the chip pins and bond wires and the electrical resistances of the buses become significant as clock rates are pushed higher and higher. Resistive voltage drops along a power supply bus from one driver to the next, and cumulatively along the length of a bus can become large enough to cause undesirable noise effects and troublesome differences in speeds or times of operation of the respective drivers on a circuit chip. These differences in speed are particularly marked when almost all of the off chip drivers are outputting binary xe2x80x9c1""sxe2x80x9d, for example, and only one or a few are outputting binary xe2x80x9cO""sxe2x80x9d (or vice versa). As clock rates are pushed higher and higher in order to realize the full benefits of high speed DRAMs, the respective times of switching amongst previously known off chip drivers on a chip differ more and more and this results in greater and greater xe2x80x9cTSSOxe2x80x9d errors. Such a situation can seriously limit proper operation of a computer, for example. It is important therefore to eliminate, or at least significantly reduce such noise effects and timing errors.
It is thus desirable to reduce the above described problems of integrated circuit off chip drivers and thus to facilitate high speed operation.
The present invention, in one illustrative embodiment, is directed to an integrated circuit having multiple off chip drivers connected to a pair of short length, higher and lower voltage buses by respective pairs of terminals, each terminal being fabricated on the chip with a resistance considerably greater than the resistance of either voltage bus. The respective resistances of the terminals are substantially equal to each other. In a typical embodiment each driver comprises an n-channel and a p-channel field effect transistor with their gates connected in common to a binary data input and their drains connected in common to an output for corresponding binary data. The respective source of the p-channel transistors is coupled to a higher voltage bus and the source of the n-channel transistor is coupled to a lower voltage bus. A first capacitor also fabricated on the IC chip is connected from the source of one transistor to the source of the other and serves along with the resistances of the pair of terminals connecting the driver to the buses to decouple to a considerable extent the operation of this driver from the operations of the other drivers on the chip. A second capacitor and a third capacitor are also fabricated on the chip along with switching means connected to them. Thus, for example, when the output is being driven positive by the driver the second capacitor, which had previously been charged from the higher voltage bus, is connected by the switching means to the output. At the same time this takes place, the third capacitor is connected by the switching means to the lower voltage bus and is pre-set with a lower voltage charge. When the output is next driven negative by the driver, the third capacitor is connected by the switching means to the output, and the second capacitor connected to the higher voltage bus and is pre-set with a higher voltage charge. This equal and opposite charging and discharging (and vice versa) of the second and third capacitors substantially reduces switching interactions and timing differences amongst the multiple off chip drivers. This permits reliable operation at higher speeds than would otherwise be possible.
From one aspect the present invention is directed to an integrated circuit comprising first and second power supply buses with a plurality of circuits coupled via conductors, which each have a resistance, between the first and second power supply buses. The resistance of each of the conductors between the circuits and the first power supply bus are essentially equal and are substantially greater than the resistance of the first power supply bus. The resistance of each of the conductors between the circuits and the second power supply bus are essentially equal and are substantially greater than the resistance of the second power supply bus.
From an other aspect, the present invention is directed to an integrated circuit comprising first and second power supply buses with a plurality of circuits coupled via conductors, which each have a resistance, between the first and second power supply buses. Each circuit comprises an input and an output and first and second capacitors. The first capacitor has a first terminal coupled between the output terminal of the circuit and a first terminal of the circuit which is coupled to a conductor which couples the circuit to the first power supply bus. The second capacitor has a first terminal coupled between the output terminal of the circuit and a second terminal of the circuit which is coupled to the conductor which couples the circuit to the second power supply bus.
From still an other aspect, the present invention is directed to an integrated circuit comprising first and second power supply buses with a plurality of circuits coupled via conductors, which each have a resistance, between the first and second power supply buses. The resistance of each of the conductors between the circuits and the first power supply bus is essentially equal and is substantially greater than the resistance of the first power supply bus. The resistance of each of the conductors between the circuits and the second power supply bus is essentially equal and is substantially greater than the resistance of the second power supply bus. Each circuit comprises an input and an output and first and second capacitors. The first capacitor has a first terminal coupled between the output terminal of the circuit and a first terminal of the circuit which is coupled to a conductor which couples the circuit to the first power supply bus. The second capacitor has a first terminal coupled between the output terminal of the circuit and a second terminal of the circuit which is coupled to the conductor which couples the circuit to the second power supply bus.
A better understanding of the invention together with a fuller appreciation of its many advantages will best be gained from a study of the following description and claims given in conjunction with the accompanying drawings.